1. Field of the Invention
The present invention relates to manufacture of a semiconductor integrated circuit, and particularly to a lithography process for forming circuit patterns employed in the semiconductor integrated circuit with satisfactory accuracy and a lithography apparatus used therein.
2. Description of the Related Art
High-performance/high-function improvements of a semiconductor integrated circuit have been achieved by micro-fabrication/high integration of circuit patterns. The semiconductor integrated circuit is formed by stacking flat or plane circuit pattern layers on one another in a vertical direction in layers. However, there is a need to perform high-accuracy layer-to-layer alignment between upper and lower circuit pattern layers in order to connect between the upper and lower circuit pattern layers. As to the accuracy of this alignment, strict value is have been increasingly, required with the micro-fabrication of the patterns. In order to achieve such a request, an attempt has been made to improve stage accuracy of an exposure equipment, position accuracy of each pattern on a mask, the sensitivity of detection of alignment marks on a wafer and a mask, etc. The progression of these alignment accuracies and methods thereof have been discussed in, for example, International Technology Roadmap for Semiconductors 1999 Edition (Semiconductor Industry Association, 1999), pp. 143-148).
On the other hand, the accuracy required for circuit pattern dimensions has also grown in severity with the micro-fabrication. There is a need to measure the critical dimensions with high accuracy to control the dimensions. Various dimension measuring techniques used for this purpose have been developed. A scanning electron microscope (SEM) is now mainly used for critical dimension measurement. The use of a scatterometry using light diffraction, an atomic force microscope (AFM), etc. has also been discussed. In particular, the scatterometry is capable of measuring sidewall angles and heights of patterns, and the thickness of an underlying film as well as pattern""s critical dimensions. The scatterometry has been discussed in, for example, Proceedings of SPIE, Vol. 4344, pp. 716-725(2001)).
Meanwhile, as the cause of degrading the accuracy of alignment of the wafer with the mask, there was a problem that a detection signal becomes asymmetric due to asymmetry of each alignment mark on the wafer and hence the position of center of the mark is not properly detected, thus resulting in the occurrence of an alignment error. Now consider where such an alignment mark 303 as shown in FIG. 2(a) by way of example, which is formed in a non-alignment layer film 302 on an underlying substrate 301, is observed and such a detection signal as indicated in a lower stage of the same drawing is obtained. When the right and left sidewall angles of the mark whose cross-sectional is to be originally symmetrical as shown in FIG. 2(a), are different from each other (FIG. 2(b)) the bottom of the mark is inclined (FIG. 2(c)), and a distribution is formed in the thickness of a film (resist film or the like) 304 for covering the corresponding mark (FIG. 2(d)), for example herein, alignment detection signals become asymmetric as shown in the same drawing respectively. It is thus difficult to determine the accurate center of the mark. Since this problem is of a problem ascribable to the wafer in which layer alignment is performed, the present problem cannot be solved by only the above improvements in the stage accuracy, the mask accuracy, the sensitivity of detection of each alignment mark, etc., and an improvement in the performance of each component in an exposure step. A method of reducing the influence of the asymmetry has been proposed for an alignment (positioning) method using a heterodyne detection method. However, it cannot be applied to an alignment method using a mark observed image based on the normal bright field or the dark field imaging method.
An object of the present invention is to provide a method of performing alignment of a mask (transfered image) and a wafer (underlying layer) with satisfactory accuracy and transferring a mask pattern even when the above-described asymmetry of each alignment mark on the wafer exists, thereby manufacturing a high-performance semiconductor device reduced in alignment discrepancy with high yields without sacrificing throughput even when circuit patterns are fine.
The above object is achieved by, in a method of manufacturing a semiconductor device, wherein a second pattern is formed by exposure or graphic-drawing in registration with a first pattern, on a resist film formed over a first pattern layer formed on a substrate, (1) measuring asymmetries of alignment marks (and their peripheries) formed within the first pattern layer, and (2) thereafter performing the alignment using the amount of offset for the alignment, based on the result of measurement. Namely, in a method of manufacturing a semiconductor device, wherein a first pattern formed on a substrate, and a mask having a second pattern or a beam for graphic-drawing the second pattern are aligned with each other, and thereafter a resist film formed over the first pattern is exposed by a projected image of the mask or the beam, thereby forming the second pattern in registration with the first pattern, asymmetry of each of alignment marks (and their peripheries) are measured prior to the alignment signal detection step, a discrepancy between the mark detection signal and a true mark center due to a step for performing the alignment and the asymmetry of the alignment mark is determined from the result of measurement, the alignment signal is corrected using the amount of offset corresponding to the discrepancy, thereby correcting an error produced due to the asymmetry to perform the alignment.
Here, the measurement of the asymmetries of the alignment marks is achieved by irradiating the alignment marks or periodic pattern features close thereto having the same structures as the alignment marks with light and measuring dependence of reflected or diffracted light intensities, a wavelength of the irradiated light on at least any one of incident angle, diffraction order, and polarization-angle of the light.
The step of measuring the asymmetry may preferably be performed during a period before the measurement of each alignment mark within an exposure equipment after the formation of the alignment marks or resist coating. Further, the asymmetry measuring step may preferably be performed within a resist coater equipment for performing the resist coating or within the exposure equipment for performing the exposure.
The step of forming the resist film, the step of measuring the asymmetry and the step of performing the alignment or the step of performing the alignment and exposure or graphic-drawing may preferably be processed for a plurality of wafers in so-called xe2x80x9cpipelinexe2x80x9d fashion.